The present invention relates to a semiconductor device, and, more particularly, the present invention relates to a technique which is effective when applied to a semiconductor device having a QFN (Quad Flat Non-leaded) package configuration.
Semiconductor devices which have a QFN (Quad Flat Non-leaded) package configuration are manufactured by mounting individual semiconductor chips on respective die pad portions (tabs) of a lead frame, wire bonding the lead portions of the lead frame to electrodes on respective surfaces of the semiconductor chips, performing resin mold encapsulation, and then cutting the lead frame into individual pieces. At the respective mounting surfaces of the semiconductor devices, each of which has in a QFN package configuration, the lead portions of the lead frame are partly exposed from the encapsulating resin so as to serve as external terminals.
Japanese Laid-Open Patent Application No. 2001-24133 discloses a lead frame which has die pad portions, each for mounting a semiconductor element within a frame body composed of a metal plate; suspended lead portions having terminal ends connected to the frame body and tip end portions for supporting a die pad portion; and land lead portions and lead portions disposed to have the tip end portions opposing the die pad portion and terminal end portions connected to the frame body. The land lead portions and the lead portions have respective bottom surfaces which form external terminals. The die pad portion has an opening in a generally central portion thereof, a plurality of support portions upwardly protruding in the open region to support a semiconductor element at the bottom surfaces thereof, and a coupling portion for coupling the plurality of support portions to each other (see Patent Document 1).
[Patent Document 1] Japanese Laid-Open Patent Application No. 2001-24133